The present invention relates in general to multi-ported logic first-in, first-out ("FIFO") structures. More particularly, the present invention relates to a system and method for efficient implementation of multi-ported logic FIFO structures of particular utility with respect to processor and other integrated circuit ("IC") design in which on-chip resources and power consumption must be optimized while facilitating operation at very high clock frequencies.
A multi-ported logic ("FIFO") is a logic block that has a certain number of ports (either "read" or "write") that follow a sequential access order of an array of entries. Each entry of the array may (or may not) have additional logic associated with it. In this regard, single-ported structures are merely a special case of multi-ported structures. Typically, a multi-ported FIFO requires a read or write of multiple entries per clock cycle.
Multi-ported FIFO structures may be used in a number of areas in a given processor or other integrated circuit design, and conventional implementations of a multi-ported FIFO include the use of a register file with head and tail pointers that are used for reading and writing to the structure. The head and tail pointers are decoded through row decoders and the word lines are then generated for the register file. The number of word lines in the register file is ultimately proportional to the total number of read and write ports for the FIFO.
As an example, a given microprocessor architecture may incorporate a branch repair table ("BRT") to resolve branch mispredicts. This structure is responsible for storing certain information about a branch that is available when the branch is fetched. This information is later accessed when the branch is resolved at execution time to determine if the branch had a mispredict. In this regard, the BRT is utilized as a FIFO and branch information is stored in it at fetch time. In a particular implementation, four branches in a fetch bundle may be written to four sequential entries in the BRT at fetch time.
A conventional implementation of the BRT might then include the provision of four 5-bit pointer registers that hold pointers for the slots that are available for writing. The first of these pointers is called the "head pointer" ("H"). Since these slots are all in sequential order, the other registers contain H+1, H+2, and H+3 respectively. Each of these pointer registers can be decoded through a 5-to-32 decoder to activate the appropriate word lines into the storage array for memory access. There may also be additional logic for updating the pointers based on a number of external control signals consisting of a number of incrementers and multiplexers ("MUX").
Such an implementation is inherently inefficient in that the array itself then requires an excessive number of word lines (32.times.4 word lines) where a smaller number of word lines would be more desirable (i.e. 32 word lines). Since most of the multi-ported logic FIFO structures in a given design are likely to be "metal limited", (that is, the die area required to implement the FIFO is constrained by the metal interconnect) this translates into a significant inefficiency in the on-chip area consumed. Moreover, outside of the storage array, the associated row decoders and pointer update logic dedicated to providing the row decode and pointer update functions also consumes an additionally undesirable amount of on-chip area.